1. Technical Field
The present invention relates in general to a method and system for modeling the behavior of a circuit and in particular to a method and system for generating a logical fault model of an integrated circuit. Still more particularly, the present invention relates to a method and system for modeling the behavior of a circuit, which automatically generate a compact logical fault model of an integrated circuit from a circuit netlist description.
2. Description of the Related Art
A state-of-the-art VLSI (Very Large Scale Integration) integrated circuit, such as a microprocessor, can include between several hundred thousand and several million transistors, as well as other circuitry, all formed within a semiconducting substrate. Conventionally, VLSI integrated circuits have been designed utilizing a "book library" approach in which an integrated circuit is subdivided into a number of functional blocks. The circuit designer then selects circuit "books" within the design library, which each contain a limited number of transistors, to perform the functions of corresponding functional blocks within the integrated circuit. Utilizing the book library design methodology is rapid and economical because books within the design library can be utilized numerous times within a particular integrated circuit and reused in the design of other integrated circuits. A further advantage of the conventional book library approach is that the behavior of the integrated circuit can easily be modelled because the fault model for each book in the design library is known. Thus, the composite fault model for an integrated circuit design can be obtained simply by combining the individual fault models for the books incorporated within the integrated circuit design.
Although the conventional book library design methodology provides a relatively rapid and automated method for integrated circuit design, the conventional book library approach does not provide the integrated circuit optimization required to achieve the increasingly aggressive timing and functional goals of state-of-the-art VLSI integrated circuits. Accordingly, fully custom designs are now frequently utilized in order to maximize integrated circuit performance and minimize the semiconductor die area required to implement the design. Currently, facilities that allow integrated circuit designers to develop custom circuit designs at the transistor level or in a hierarchical circuit description are provided in commercially available VLSI design tools. VLSI design tools permit a circuit designer to perform circuit simulation and optimization to accomplish a custom design based upon a schematic entry of the components and interconnections within the integrated circuit. Furthermore, some VLSI design tools advantageously include facilities for testing the reliability and accuracy of the integrated circuit design.
Conventionally, testing an integrated circuit requires the construction of a logical fault model of the integrated circuit and the generation of a minimal set of test patterns to stimulate the circuit such that detectable faults can be exercised. Logical fault models are utilized since the number of possible different failures within the integrated circuit makes individual analysis of failures infeasible. Thus, failures are grouped together according to the logical effect of the faults on the functionality of the integrated circuit. Although it is known in the art to automatically generate a logical fault model of a VLSI integrated circuit from a circuit netlist, such logical fault models typically employ a complex set of heuristics to determine equations which represent integrated circuit behavior. Because of the complexity of the circuit analysis performed by conventional automatic logical fault model generators, the application of conventional automatic logical fault model generators to custom-design integrated circuits including millions of transistors is too computation-intensive to be practical.
As should thus be apparent, an improved method and system for generating a fault model for a VLSI integrated circuit is needed which automatically generates a compact logical fault model of a VLSI integrated circuit from an input circuit netlist.